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代寫ELE00013M 代寫Field-Programmable Gate Array



Department of Electronic Engineering

Assessments 2019/20

ELE00013M
Embedded Systems for Field-Programmable Gate Array


There are two components to this assessment.

Unless the assessment specifies a group submission, you should assume all submissions are
individual and therefore should be your own work.

Oral Presentation - contributes 30% of the assessment for this module. Clearly indicate your
name on every separate piece of work submitted. The in-class presentation which will take
place on 11/03/20 (SpT Wk 10 Wed).
Please note that you are expected to submit a zip file containing slide handouts/notes via the
VLE by 12 noon on 09/03/20 (SpT Wk 10 Mon).
Report - contributes 70% of the assessment for this module. Clearly indicate your examination
number on every separate piece of work submitted. Submission is via the VLE and is due by 12
noon on 14/04/20 (SuT Wk 1).

Please try and submit early as any late submissions will be penalised.

Please remember that if this is your first year of study, you need to complete the mandatory
Academic Integrity Tutorial http://www.york.ac.uk/integrity/



ELE00013M
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UNIVERSITY OF YORK
Department of Electronic Engineering
Embedded Systems using FPGA Assessment 2019/20
Lecturer: Dr Ruwan Gajaweera
1. Design task: Multifunction Digital Clock
Your assessment task for this module is to design, implement and test a multifunction digital clock.
The next laboratory session will give you time to work on your design with assistance from the
demonstrators.

As in the previous labs you will use the ZedBoard as a platform for investigating and implementing
your embedded system design. You can choose the functions you wish to implement as long as
the following requirements are met:
Requirements
● You must design and implement at least one peripheral of your own in VHDL.
● The software design must make use of at least one interrupt.
Information
● You may use a suitable display (using HDMI connectivity or OLED panel) for the clock.
● You may make use of various pushbutton switches, DIP switches and LEDs that are
available on the ZedBoard, to create a user-friendly device. If you use any of the
pushbutton switches, adequate precautions need to be taken in order to avoid switch
bounce.
● You may use an operating system if you wish.
● You may use the Processor System in the Zynq for your design.
● Any of the other features available on the development board may be used.
● You may use the buzzer unit provided to you.
● Your system may boot from an SD card
2. Specification ideas
Digital clock main functions:
● Display current time
● Alarm facility
● Stopwatch
● Timer
Clock display:
● Selectable 12/24 hour display
● Display hours/minutes/seconds
● Alarm set/not set
ELE00013M
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Clock facilities:
● Set time
● Alarm with ‘Snooze’ function
● Low power sleep function
Stopwatch facilities:
● Start stopwatch
● Stop stopwatch
● Clear stopwatch
Timer function:
● Set time (hours, minutes and seconds)
● Start timer
● Indicate visually and audibly the end of the set time period
3. Your design task
From the specification ideas in Section 2, choose the functions you wish to design and
implement. The number of functions you choose and their complexity will be entirely up to you.

Choose your functions wisely: You should initially be conservative in the number of functions you
choose and their associated complexity. It is better to submit a working, completed result rather
than lots of partially designed fragments. You will be able to add more functions to your design
choice at a later date if time permits.

If you feel that the list given in Section 2 is lacking some functionality that you want to include
then you are welcome to add them into your final design.
4. Assessment
This design task will form part of your overall module assessment in two ways:
1. You will be expected to give a short presentation on your design during the laboratory
session in week 10. Your design should be well developed by then, but the implementation
does not have to be completed and working. You should submit a zip file containing the
slides and notes for the presentation to the VLE by 12:00 noon on Monday week 10.
2. You will also submit a formal report on your completed design at the beginning of next
term. Further details of the report and presentation are provided below in sections 5 and
6.
4.1 Resources and Hints
● You may find that the schematic for the ZedBoard is useful. You can find this, along with
other support materials at:
http://www.zedboard.org

ELE00013M
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● Try to design a product, rather than simply choosing a list of features to implement. What
will your device do?
● You may make use of existing Xilinx IP cores if you like.
● Marks will be awarded for careful, well-justified design decisions. Break your features down
into requirements on individual tasks, then think carefully about which of your features you
will implement in hardware, and which in software. Does your selection of software tasks
justify using an operating system? In software, is the CPU used wisely (by using interrupts,
for example) or is much of its power wasted by waiting in polling loops or blind waits?
4.2 Academic conduct
● This is an individual assignment; you MUST work on your own. You are welcome to consult
any sources of information you can find as long as you provide appropriate reference and
attribution to the authors. If you use code written by anybody else (including your lecturers)
you must make it clear which part is yours and which has been written by the other person.
You should make this clear both in your report and in the code itself.
● Please note that MSc students are required to complete the academic integrity tutorial
here:
http://www.york.ac.uk/integrity/
● If the rules on what constitutes correct academic conduct are not clear, please consult
section 5.7 of the university rules and regulations here: 5.7 Academic misconduct. The
department guidance on plagiarism can also be found here: Electronics plagiarism page.
NOTE: The assessors reserve the right to viva students on their submissions.
4.3 Submission of reports
Report submission will be electronic via the VLE in two parts:
1. A PDF report (no more than 1500 words).
2. A zip file containing the complete source code for your program (fully commented and
properly indented). This should be the whole of your Xilinx project including the boot image
(if the system can be booted from an SD card) so that the assessor can test your design.
It is highly recommended that, prior to submitting, you unzip your zip file and see if your
project can be opened using relevant software and implemented on a ZedBoard in one of
the departmental laboratories. Please note that there is a mark allocation for the quality
and the functionality of the project files you submit along with the report under the
“Technical Merit” attribute (see section 5).
PLEASE NOTE: Anonymised marking - use your exam number only
Marking will be done anonymously so DO NOT put your name on or in any of the submission
parts. Instead, your report, code comments and filenames should identify you using your exam
number only.
5. Laboratory report details
You are expected to submit a short formal technical report related to the design work you have
undertaken on the digital clock task.
ELE00013M
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Aims and objectives
The principal aim of this technical report is to enable you to further develop your communication
skills in the practice of formal technical report writing and to assess your learning from this module.
It is vital that you remember the purpose and learning outcomes of this module when writing your
report. You should present your design decisions logically and clearly.
Content of the report
The report needs to be clear, concise and to the point. As a minimum it should include:
● A description of the functions designed
● A detailed specification of the functions designed
● How the functions relate to the complete digital clock system
● Details of the design decisions you made
● What resources you used
● How you tested your design
● Any problems you encountered
● A user guide for your product, no more than a page in the appendix
Format of the report
This is a formal report so it should include:
● Abstract/summary
● Contents page
● An introduction
● The main body of the report, suitably structured
● Conclusions
● References
● Appendices
Your report should be no longer than 1500 words excluding the appendix.

ELE00013M
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Indicative mark scheme

Part Mark
Abstract/summary 5%
Contents/Introduction 10%
Presentation 20%
Technical merit 60%
Conclusions 5%
The report is worth 70% of your module mark.
6. Presentation details
During the laboratory session in week 10, you will be required to give a short presentation related
to your functional design work associated with the digital clock project. When you are not
presenting, you will be expected to listen quietly to the other presentations, but you may also
continue to work on implementing and testing your system.

Duration: 5 minutes.
Method: PowerPoint slides or equivalent.
Content:
As a minimum you should provide details of the device you have designed, particulars of the
resources you have used (for example processors and peripherals), an overview of your software
and hardware design process, and information about any problems you have encountered.

We won’t be expecting you to have completed the implementation of your design, but we will
expect you to have completed your hardware and software designs, and started the
implementation.
Additional Information:
Make sure your presentation has a clear introduction and conclusion, that you use your slides
effectively, that the technical content is appropriate and accurate, and that it is the right length.
The schedule of presentations may not be available until the laboratory session itself. Whether or
not the schedule is available beforehand, you must be present for the entire session.

This assessment is worth 30% of your overall module mark, and your presentation will be marked
by at least two people.

Criteria Mark
Audibility 10%
Slide design and layout 10%
Presentation structure 10%
Design features 30%
Technical content 30%
Preparation 10%

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